A SPICE model of silicon tunneling field-effect transistors

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초록

In this study, we propose a precise model of silicon tunneling field-effect transistors (TFETs) by modifying the Kane-Sze tunneling formula. In our model, a reference device is calibrated by utilizing TCAD and SPICE simulation. Electrical parameters extracted in our TCAD simulation are applied to a SPICE model not only for adopting the off-state current of a p-i-n diode under a reverse bias state but also for developing the threshold voltage and electric field equations. Furthermore, a basic complementary TFET inverter is simulated to demonstrate the capabilities of our proposed model. (C) 2018 Elsevier B.V. All rights reserved.

키워드

Tunnel FET; Calibration; TCAD simulation; SPICE model; Device modeling; GATE; FETS
제목
A SPICE model of silicon tunneling field-effect transistors
저자
Woo, Sola; Kim, Minsuk; Kim, Sangsig
DOI
10.1016/j.mee.2018.01.028
발행일
2018-05-05
유형
Article
저널명
Microelectronic Engineering
권
191
페이지
66 ~ 71