A 0.3V-V-IN, 0.015ps-FoM Fully Integrated Analog-Assisted Digital LDO With Dual-Negative Gate Control and Adaptive Transient Recovery Path

초록

This letter presents a fully integrated analog-assisted (AA) digital low-dropout regulator (DLDO) to operate at low input voltage (V-IN) with fast transient response. A negative voltage gate driver (NVGD) enables low-V-DS triode operation and large current capacity of pass transistors even at low V-IN of 0.3 V by utilizing a negative voltage. Adual negative voltage tank(DNVT) compensates for leakage in NVGD for reliable output regulation. An adaptive transient recovery path (ATRP) in AA loops expedites output voltage (V-OUT) regulation against a large load current (I-LOAD) step. The negative supply fromDNVTalso enhances inverter-based comparators in ATRP at low V-IN. The proposed DLDO fabricated in a 28 nm complementary metal-oxide-semiconductor (CMOS) process operates at lowest V-IN of 0.3-1 V with 50 mV dropout among state-of-the-art DLDOs. The DLDO consumes quiescent current of 23 mu A, while providing large I-LOAD up to 800 mA. The ATRP ensures small V-OUT droop of 97 mV against Delta ILOAD of 380 mA, achieving a low figure-of-merit (FoM) of 0.015 ps.

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