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A Simple Method for Estimation of Silicon Film Thickness in T-Gate Junction less Transistors
- Jeon, Dae-Young;
- Park, So Jeong;
- Mouis, Mireille;
- Barraud, Sylvain;
- Kim, Gyu-Tae;
- 외 1명
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1초록
Junction less transistors (JLTs) without PN-junctions near the source/drain are promising candidates for further development of CMOS technology. The Si thickness of tri-gate JLTs is crucial to understand their unique electrical properties related to bulk neutral and surface accumulation conduction. A simple method based on a unique operation mechanism is suggested for extraction of t(si) from measurements on tri-gate JLTs. The method was successfully applied to fabricated tri-gate JLTs and the extracted t(si) values were comparable with those of transmission electron microscopy. Furthermore, the validity of the method was confirmed by 2-D numerical simulation.
키워드
Junctionless transistors (JLTs); Si thickness (t(si)); bulk neutral channel; surface accumulation channel; method for parameter extraction; numerical simulation; NANOWIRE TRANSISTORS; CHANNEL WIDTH
- 제목
- A Simple Method for Estimation of Silicon Film Thickness in T-Gate Junction less Transistors
- 저자
- Jeon, Dae-Young; Park, So Jeong; Mouis, Mireille; Barraud, Sylvain; Kim, Gyu-Tae; Ghibaudo, Gerard
- 발행일
- 2018-09
- 유형
- Article
- 권
- 39
- 호
- 9
- 페이지
- 1282 ~ 1285