A new method for the extraction of flat-band voltage and doping concentration in Tri-gate Junctionless Transistors

  • Jeon, D. -Y.; 
  • Park, S. J.; 
  • Mouis, M.; 
  • Barraud, S.; 
  • Kim, G. -T.; 
  • 외 1명
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초록

A new method for the extraction of flat-band voltage (V-fb) and channel doping concentration (N-d) in Tri-gate Junctionless Transistors (JLTs) is presented. The new method, based on the relationship between the top-effective width (W-top_eff) in accumulation and the effective width (Weir) in partial depletion, enables the extraction of V-fb, and Nd of JLT devices (here as approximate to 0.61 V and approximate to 6.4 x 10(18) cm(-3), respectively). The validity of the new method is also proved by 2D numerical simulations. Furthermore, it is emphasized that the sidewall accumulation current (I-d_side) behavior of Tri-gate JLT devices is found to decrease dramatically near Vfb, allowing an estimation of the V-fb position of JLT devices. (C) 2013 Elsevier Ltd. All rights reserved.

키워드

Junctionless Transistors (JLTs); Extraction method; Flat-band voltage (V-fb); Doping concentration (N-d); Effective width (W-eff); 2D numerical simulation; Sidewall accumulation current (I-d_side); NANOWIRE TRANSISTORS
제목
A new method for the extraction of flat-band voltage and doping concentration in Tri-gate Junctionless Transistors
저자
Jeon, D. -Y.; Park, S. J.; Mouis, M.; Barraud, S.; Kim, G. -T.; Ghibaudo, G.
DOI
10.1016/j.sse.2012.11.011
발행일
2013-03
유형
Article
저널명
Solid-State Electronics
권
81
페이지
113 ~ 118