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A 1.3V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system
- Min, Young-Jae;
- Jeong, Chan-Hui;
- Moon, Junil;
- Han, Youngsun;
- Kim, Soo-Won;
- ... Kim, Chulwoo
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0초록
A fast transient-response digital low-dropout regulator ( D-LDO) is presented. To achieve fast-transient time, a VSSa generator and a coarse-fine power-MOS array techniques are proposed. The proposed D-LDO is implemented in a 65 nm CMOS technology with a die area of 0.067 mm(2). The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5mA to 120 mA, and the step-down time is 0.1 us at 1.2V of supply voltage. Moreover, the voltage spikes are less than 190mV.
키워드
low-dropout (LDO) regulator; digital low-dropout (D-LDO) regulator; fast-transient-response time; dynamic voltage frequency scaling (DVFS); LOW-QUIESCENT CURRENT; FREQUENCY COMPENSATION SCHEME; VOLTAGE
- 제목
- A 1.3V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system
- 저자
- Min, Young-Jae; Jeong, Chan-Hui; Moon, Junil; Han, Youngsun; Kim, Soo-Won; Kim, Chulwoo
- 발행일
- 2017-07-10
- 유형
- Article
- 권
- 14
- 호
- 13
- 언어
- ENG
- 출판사
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- 발행국가
- 일본
- ISSN
- P 1349-2543