A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC

초록

An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-mu m CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 mm(2) consumes 12 mA and its measured jitter is 4 ps(rms) at 2.4 GHz.

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