Impedance Optimization of Power Delivery Networks with a Reduced Number of Decoupling Capacitors Using a Hierarchical Genetic Algorithm for via and Capacitor Co-Design

  • Song, Suhyoun; 
  • Chung, Ook; 
  • Son, Jungil; 
  • Nam, Seungki; 
  • Moon, Sungwook; 
  • ... Lee, Jaehoon
Citations

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초록

Optimizing the positions of decoupling capacitors (decaps) is critical for the design of power delivery networks (PDNs). Conventional methods typically employ fixed via positions, limiting design flexibility and often yielding suboptimal impedance performance. This study proposes a hierarchical genetic algorithm that simultaneously optimizes via positions and decap positions and types to achieve the target impedance while reducing the number of decaps used. The proposed method first selects via positions over a large search space, and the decap optimization is subsequently conducted on the selected vias. A precomputed inductance look-up table (LUT) is employed to accelerate impedance calculation during the iterative optimization process. The simulation and measurement results validate the accuracy of the impedance estimation and demonstrate that the proposed co-design method achieves the target impedance, which the conventional fixed-via method fails to satisfy. This study highlights the importance of considering via and decap co-design in practical PDN optimization.

키워드

boundary element method; decoupling capacitor; genetic algorithm; look-up table; power delivery network; power integrity; via optimization; PLANES
제목
Impedance Optimization of Power Delivery Networks with a Reduced Number of Decoupling Capacitors Using a Hierarchical Genetic Algorithm for via and Capacitor Co-Design
저자
Song, Suhyoun; Chung, Ook; Son, Jungil; Nam, Seungki; Moon, Sungwook; Lee, Jaehoon
DOI
10.3390/electronics15163523
발행일
2026-08-08
유형
Article
저널명
Electronics (Basel)
권
15
호
16