An 8-bit 400-MS/s 1-then-2-bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration

초록

This letter presents an 8-bit 400 MS/s 1-then-2-bit/cycle SAR ADC employing a comparator rotation-based background offset calibration (CRBC) technique. Unlike conventional 1-then-2-bit/cycle architectures, where calibration validity depends on the input voltage, the proposed CRBC enables input-independent background calibration, ensuring rapid calibration convergence and the reliable detection of time-varying errors, irrespective of input conditions. The prototype ADC was fabricated in 28 nm CMOS technology and achieves a signal-to-noise-and-distortion ratio (SNDR) of 42.9 dB and a spurious-free dynamic range (SFDR) of 56.5 dB at the Nyquist frequency. It consumes 1.67 mW at 400 MS/s, resulting in a Walden figure-of-merit (FoM<inf>W</inf>) of 36.6 fJ/conversion-step. © 2025 Elsevier B.V., All rights reserved.

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