A 101.6-dB-SNDR Fully Dynamic Zoom ADC Using Miller-Compensated Floating Inverter Amplifiers

  • Choi, Yohan; 
  • Lee, Woojin; 
  • Park, Sooho; 
  • Kim, Changjoo; 
  • Jung, Hyundo; 
  • ... Kim, Chulwoo
Citations

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11
Citations

SCOPUS

20

초록

This brief presents a fully dynamic zoom analog-to-digital converter (ADC) using a Miller-compensated two-stage floating inverter amplifier (MCFIA). Due to the two-stage design, the proposed MCFIA achieves a sufficient gain for a high-resolution delta-sigma modulator design. Compared to the conventional two-stage design, the stability criterion of MCFIA is advantageous in driving bigger sampling capacitors needed to reduce kT/C noise. Moreover, a zoom ADC architecture mitigates the swing range requirement of the MCFIA. A prototype ADC was implemented in a 180-nm CMOS process and achieved a signal-to-noise and distortion ratio (SNDR) of 101.6 dB with an SNDR-based Schreier figure-of-merit of 174.8 dB at a sampling frequency of 2.56 MHz.

키워드

Capacitors; Circuits; Circuit stability; Noise; Timing; Three-dimensional displays; Stability criteria; Analog-to-digital converter (ADC); dynamic amplifier; floating inverter amplifier; fully dynamic ADC; Miller compensation; zoom ADC; SAR ADC
제목
A 101.6-dB-SNDR Fully Dynamic Zoom ADC Using Miller-Compensated Floating Inverter Amplifiers
저자
Choi, Yohan; Lee, Woojin; Park, Sooho; Kim, Changjoo; Jung, Hyundo; Kim, Chulwoo
DOI
10.1109/TCSII.2024.3392909
발행일
2024-09
유형
Article
저널명
IEEE Transactions on Circuits and Systems II: Express Briefs
권
71
호
9
페이지
4141 ~ 4145