An Error Compensation Technique for Low-Voltage DNN Accelerators

초록

Reducing supply voltages of deep neural network (DNN) accelerators has been of particular interest since it can achieve high energy efficiency for mobile/edge applications. To ensure reliable DNN operations at low voltage, improving the timing error resilience of DNN accelerator is highly required. In this article, we present an error resilient technique to support low-voltage DNN operations by detecting and compensating erroneous computations using the proposed compensation multiply-accumulate (CMAC) unit. First, the timing errors are detected using Razor flip-flops at critical data-path, and erroneous computations are identified and dumped. Using additional multiplier data-path with flip-flops, the dropped computations are compensated in the next CMAC unit without additional clock-cycle penalty. Various bit-precisions of error compensations are analyzed to efficiently tradeoff DNN accuracy and hardware overhead. To improve the DNN accuracy even at low bit-precision of compensation, two types of rounding techniques are presented to effectively reflect the actual distribution of DNN computation results. The low-voltage DNN accelerator based on the proposed error compensation scheme has been implemented using 65-nm CMOS. Post-layout simulations show that the proposed DNN accelerator for ResNet-18 achieves about 47% and 24% energy savings compared with baseline and state-of-the-art error resilient DNN accelerators, respectively.

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