A 6.1-to-41.5 GHz CMOS Low-Noise Amplifier for Wideband and Highly Linear Applications

초록

This paper presents a CMOS low-noise amplifier (LNA) for wideband applications that require high linearity. A frequency staggering technique is employed to achieve a flat gain response over a wide frequency band. In the first stage, the LNA uses a common-source topology with resistive feedback to achieve wideband input matching, while inductive series peaking is adopted at the output to attain gain peaking at a high frequency. In the second stage, an inductive load with high inductance is employed to ensure low-frequency gain and high linearity. Furthermore, the bias condition of the transistors is optimized by considering the trade-off between linearity and DC power consumption. The proposed LNA achieved a measured peak gain of 10.5 dB at 18 GHz and a wide 3-dB bandwidth ranging from 6.1 to 41.5 GHz. The third-order intercept point exceeded 1.3 dBm, and the input matching remained below-8 dB over the entire 3-dB bandwidth. Furthermore, the noise figure ranged from 4.7 to 7.3 dB up to 26.5 GHz.

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