MOSFET Layout Design for High-Gain Amplifiers at mm-Wave and Sub-Terahertz

초록

The parasitic capacitance and resistance originated from interconnect metals of MOSFETs degrade the high-frequency performance, including gain and bandwidth. The degradation is exacerbated as the frequency increases toward the mm-wave and sub-terahertz band. Fortunately, the adverse effect of parasitic capacitance can be relieved by circuit design techniques such as reactive impedance matching and neutralization. However, the parasitic resistance, particularly at the gate, causes loss and gain degradation, which is not easily compensated at the circuit level. In this work, the gate resistances induced by interconnect metals of two different gate feed structures are compared, which yields a layout suitable for the mm-wave and sub-terahertz band. It is experimentally confirmed that the proposed layout for a gate width of 20-60 mu m lowers the gate resistance by 10%-19.4% and consequently increases the device f(MAX) by 12.6%-23.9% compared to a reference layout. In addition, two D-band single-stage amplifiers, each using the proposed or reference layout, are compared to verify the circuit-level benefit. The measured peak gain is improved by 1.6 dB at 133 GHz due to the reduced gate resistance.

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