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-0.95V Substrate Bias Generator for Leak Power Reduction of 0.5V Digital Logic Circuits

  • Soo-Won Kim
제목
-0.95V Substrate Bias Generator for Leak Power Reduction of 0.5V Digital Logic Circuits
저자
Soo-Won Kim
학회명
ITC-CSCC
개최국가
태국
학회 개최일
2006-07-10 ~ 2006-07-13

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