Near threshold voltage digital PLL using low voltage optimised blocks for AR display system

초록

In this work, a digital phase-locked loop (DPLL) is proposed for the low power and stable operation in an augmented reality (AR) display system. The AR display system which needs the ultra-low power consumption adopts the near-threshold voltage (NTV) operation in both digital and analogue blocks. The NTV region has the advantage of small power dissipation with low-supply voltage. However, it suffers from performance degradation due to a large delay, slow transition time, and small dynamic voltage range. To achieve the optimised power efficiency and stable performance, the dynamic time-to-digital converter and the low voltage optimised digitally controlled oscillator are applied in the proposed DPLL. In addition, the forward body biasing scheme is used to increase the operation frequency for the sigma-delta modulator block. The proposed DPLL is fabricated using 65 nm CMOS technology and shows a current consumption of 160 mu A at a voltage of 0.55 V. In addition, the jitter characteristic shows 6.7 ps rms jitter and 50 ps peak to peak jitter at 480 MHz.

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