STT-MRAM-based Near-Memory Computing Architecture with Read Scheme and Dataflow Co-Design for High-Throughput and Energy-Efficiency

초록

Spin transfer torque magnetic random access memory (STT-MRAM)-based near-memory computing (NMC) architecture has been actively studied due to its potential for high-throughput and energy-efficient processing of AI algorithms. However, the low read bandwidth of STT-MRAM limits improvements in throughput of NMC architecture by failing to provide enough data to digital logic located near memory arrays. In this paper, we propose reference voltage recycling read scheme (RRS) and hybrid stationary dataflow scheme (HDS) to address the low read bandwidth issue in STT-MRAM. The proposed RRS allows for the recycling of previously developed reference bit-line voltage in a memory array during sequential read operations, enhancing read bandwidth as well as energy-efficiency of STT-MRAM. In addition, HDS balances the demand for input and weight data in digital logics located near memory arrays, facilitating full utilization of digital logics despite the limited read bandwidth of STT-MRAM. As a result, this approach can improve throughput of NMC architecture. The simulations using a 28nm CMOS process show that the proposed STT-MRAM-based NMC architecture can achieve TOPS/W of 8.45 and TOPS/mm2 of 1.37 with 8-bit input and weight, regardless of the data patterns. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

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