Fermi-Level Unpinning Using a Ge-Passivated Metal-Interlayer-Semiconductor Structure for Non-Alloyed Ohmic Contact of High-Electron-Mobility Transistors

  • Kim, Seung-Hwan; 
  • Kim, Gwang-Sik; 
  • Kim, Jeong-Kyu; 
  • Park, Jin-Hong; 
  • Shin, Changhwan; 
  • ... Yu, Hyun-Yong; 
  • 외 1명
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SCOPUS

15

초록

We demonstrate the use of germanium passivation in conjunction with a ZnO interlayer in a metal-interlayer-semiconductor structure in a source/drain (S/D) contact. The Fermi-level pinning problem resulting in the large contact resistances in S/D contacts is effectively alleviated by inserting a thin Ge passivation layer and a ZnO interlayer, passivating the GaAs surface and reducing the metal-induced gap states on the GaAs surface, respectively. The specific contact resistivity for the Ti/ZnO/Ge/n-GaAs (similar to 2 x 10(18) cm(-3)) structure exhibits a similar to 1660x reduction compared with that of a Ti/n-GaAs structure. These results suggest that the proposed structure shows promise as a nonalloyed ohmic contact in high-electron-mobility transistors.

키워드

Fermi level unpinning; gallium arsenide; germanium; specific contact resistivity; passivation
제목
Fermi-Level Unpinning Using a Ge-Passivated Metal-Interlayer-Semiconductor Structure for Non-Alloyed Ohmic Contact of High-Electron-Mobility Transistors
저자
Kim, Seung-Hwan; Kim, Gwang-Sik; Kim, Jeong-Kyu; Park, Jin-Hong; Shin, Changhwan; Choi, Changhwan; Yu, Hyun-Yong
DOI
10.1109/LED.2015.2453479
발행일
2015-09
유형
Article
저널명
IEEE Electron Device Letters
권
36
호
9
페이지
884 ~ 886