A 13.56-MHz 93.5%-Efficiency Optimal On/Off Timing Tracking Active Rectifier With Digital Feedback-Based Adaptive Delay Control

초록

This paper presents an adaptive active rectifier with digital feedback delay controllers (DFDC) which quickly tracks optimal on/off timing against input voltage and load variations. To efficiently generate the on/off transition, the proposed active rectifier adopts dynamically controlled coarse/fine delay lines rather than using conventional power-hungry static comparators, while removing the risk of unwanted multiple driving pulses to pass transistors. DFDC conducts the dual-loop digital feedback to independently adjust on/off timing with high-speed 13.56-MHz loop bandwidth, improving the voltage conversion ratio (VCR) and power conversion efficiency (PCE). DFDC can enable real-time power-saving mode control that automatically masks clock-toggling to non-essential blocks to minimize dynamic power loss while driving power transistors. To validate the efficacy of the proposed adaptive rectifier during digital feedback and settling procedures, experiments were carried out with 0.25 mu m CMOS prototype at the carrier frequency of 13.56-MHz, input voltages between 1.7 and 2.6 V, and load ranges from 0.33 to 2.2 k Omega. The proposed active rectifier employing DFDC achieves a peak PCE of 93.5% and the peak VCR of 96.3% at the output power of 12.52 mW and 2.02 mW, respectively.

키워드