Fault Bounding On-Die BCH Codes for Improving Reliability of System ECC

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초록

While continuous dynamic random access memory (DRAM) scaling may require an on-die error correction code (ECC) with enhanced correction capability, a double error correcting code with fault bounding scheme has not been explored. In this brief, we present the fault bounding on-die Bose-Chaudhuri-Hocquenghem (BCH) code that improves the compatibility with one-symbol error correcting system ECC used in dual data rate five (DDR5) dual in-line memory module (DIMM). By modifying the H matrix of BCH code, the proposed decoding method determines the fault boundary within which burst errors occur, effectively preventing the spread of these errors across fault boundaries. A comparison of bounded rates with conventional codes illustrates the enhanced compatibility with system ECC. The encoder and decoder of the proposed code have been implemented using a 28-nm CMOS process to demonstrate the hardware cost.

키워드

Error correction codes; Decoding; Symbols; Random access memory; Computer architecture; Very large scale integration; Memory modules; Performance evaluation; Hardware; Government; Aliasing; Bose-Chaudhuri-Hocquenghem (BCH) code; compatibility; dual data rate five (DDR5) dual in-line memory module (DIMM); error correction code (ECC); fault bounding; on-die ECC; Reed-Solomon (RS) code; system ECC
제목
Fault Bounding On-Die BCH Codes for Improving Reliability of System ECC
저자
Kang, Seongyoon; Shin, Chaehyeon; Park, Jongsun
DOI
10.1109/TVLSI.2024.3523899
발행일
2025-01-08
유형
Article; Early Access
저널명
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
권
33
호
5
페이지
1482 ~ 1486