Full split C-V method for parameter extraction in ultra thin BOX FDSOI MOS devices

Shin, Minju; Shi, Ming; Mouis, Mireille; Cros, Antoine; Josse, Emmanuel; Kim, Gyu-Tae; Ghibaudo, Gerard

doi:10.1016/j.sse.2014.04.039

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Full split C-V method for parameter extraction in ultra thin BOX FDSOI MOS devices

Shin, Minju;
Shi, Ming;
Mouis, Mireille;
Cros, Antoine;
Josse, Emmanuel;
... Kim, Gyu-Tae;
외 1명

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초록

The feasibility of full split C-V method in ultra-thin body and BOX (UTBB) FDSOI devices is demonstrated, emphasizing the usefulness of gate-to-bulk capacitance. The split C-V measurements carried out on both gate-to-channel and gate-to-bulk mode are shown to be consistent with TCAD simulation. This enabled us to propose an improved parameter extraction methodology for the whole vertical FDSOI stack from gate to substrate using back biasing effect. (C) 2014 Elsevier Ltd. All rights reserved.

키워드

SOI; Split CV; UTBB; MOS; MOSFETS

제목: Full split C-V method for parameter extraction in ultra thin BOX FDSOI MOS devices

저자: Shin, Minju; Shi, Ming; Mouis, Mireille; Cros, Antoine; Josse, Emmanuel; Kim, Gyu-Tae; Ghibaudo, Gerard

DOI: 10.1016/j.sse.2014.04.039

발행일: 2014-09

유형: Article

저널명: Solid-State Electronics

권: 99

페이지: 104 ~ 107

언어: ENG

출판사: PERGAMON-ELSEVIER SCIENCE LTD

발행국가: 영국

분량: 4 페이지

ISSN: E 1879-2405
P 0038-1101