Ternary half adder comprising reconfigurable triple-gated feedback field-effect transistors

초록

Ternary half adders have emerged as representative building blocks for ternary arithmetic operations, which can efficiently process large amounts of data. In this paper, we present a ternary half adder by cascading reconfigurable logic-in-memory (R-LIM) cells that perform both CONS and ANY logic functions in the same cell configuration. Each R-LIM cell is composed of eight triple-gated feedback field-effect transistors (TG FBFETs) reconfigured in n-orp-channel modes. In a R-LIM cell, the CONS and ANY gates operate with low average power consumption of 0.03 and 3.85 nW, respectively, owing to TG FBFETs exhibiting low current levels (similar to 10(-12) A) at a control gate voltage of 0 V in both the n-and p-channel modes. Furthermore, the ternary half adder retained the logic output during the hold operation for 10 ms under zero-bias conditions. The ternary half adder proposed in this study demonstrates the potential of ternary logic elements in data-intensive applications.

키워드