ScholarWorks@Korea University: Park, Jong sun

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Park, Jong sun (박종선)

College of Engineering (School of Electrical Engineering)

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Tel 02-3290-4827
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SRAM:5||Switches:3||Internet of Things:3||onchip learning:3||voltage controlled oscillator:3||domain wall memory:3||spintronics:3||wireless power transfer (WPT):3||Hardware:3||convolutional neural network:3||Computer architecture:3||spiking neural network:3||Magnetic tunneling:3||embedded memory:3||mobile DRAM:3||H.264:3||generator:2||fast Fourier transform (FFT):2||magnetic resonant coupling:2||reconfigurable architecture:2||energy efficiency:2||energy beamforming:2||timing error resilient accelerator:2||Viterbi decoder:2||BoseChaudhuriHocquenghem (BCH) decoder:2||QR decomposition:2||energyefficient accelerator:2||Beamforming antenna:2||MIMO:2||Synapses:2||voltage scaling:2||magnetic field shaping:2||charge pump:2||CORDIC:2||sensing margin:2||quantization:2||lowvoltage DNN accelerator:1||1bit synapse weights:1||Deep neural network resilience:1||DRAM:1||hardware efficiency:1||Canny edge detector:1||FIFO:1||Access disturb margin (ADM):1||Assist:1||connectivity:1||Digital signal processor:1||Wireless memory:1||Implants:1||Hybrid CMOS inverter:1||Error control code:1||Guaranteed throughput:1||resource optimization:1||Givens rotation:1||LU triangularization:1||Chromatic dispersion:1||Polarization mode dispersion:1||Wireless USB:1||UWB:1||ultra wideband:1||Discrete cosine transform:1||ternary CAM (TCAM):1||Layout:1||Capacitance:1||Magnetization:1||Memory management:1||Timedomain analysis:1||Random access memory:1||dualdomain:1||Rank order coding:1||Unsupervised learning:1||Neural Processors:1||spike timing dependent plasticity (STDP):1||Axons:1||hardware accelerator:1||SOT magnetic random access memory (SOTMRAM):1||activation sparsity:1||Variable ECC:1||Ncurve:1||VMIN:1||shared bitline:1||nearthreshold voltage:1||folded Galoisfield (GF) multiplier:1||graphene:1||static random access memory (SRAM):1||authentication:1||Deltasigma (Delta Sigma) modulator:1||Applicationspecific memory:1||eDRAM:1||cache program:1||multistage interconnection network:1||permutation network:1||pipelined circuitswitching:1||guaranteed throughput:1||onchip switch:1||H.264 systems:1||lowpower static randomaccess memory (SRAM):1||subthreshold logics:1||복수 개의 기준 성분:1||noise:1||voltage doubler:1||thinfilm transistor:1||pixel:1||OLED:1||Inter symbol interference equalization:1||high rate WPAN:1||resource allocation:1||Low computational complexity:1||model compression:1||charge domain compute:1||Spin orbit torque magnetic random access memory (SOTMRAM):1||memory cell area:1||Neurons:1||AI Processors:1||sparse coding:1||unsupervised learning:1||magnetic circuits:1||dataaware backup scheme:1||lowarea backup signal generator:1||write power reduction:1||line buffer:1||optimization:1||wireless power antenna:1||unequalerrorprotection (UEEP):1||analytics:1||high resolution:1||maximum likelihood detection:1||RFID:1||reference voltage generator:1||Special issues and sections:1||solidstate drive:1||Multidimensional CORDIC:1||Low power operation:1||circuitswitched:1||source synchronous:1||multiband orthogonal frequencydivision multiplexing (MBOFDM):1||low power filter:1||Activematrix organic lightemitting diode (AMOLED):1||clock generator:1||digitally controlled oscillator (DCO):1||Charge pump:1||highperformance CORDIC:1||SRAM failure analysis:1||onchip router:1||data permutation:1||Low power design:1||MIMO spatial multiplexing:1||Distributed Reservation Protocol:1||Mobility Support:1||Mobile IP:1||TCP:1||reference voltage:1||bit reconfigurable SARADC:1||stochastic spiketimingdependent plasticity:1||Inmemory computing:1||CNN Accelerator:1||Binarized neural network:1||dataaware backup technique:1||energy saving:1||neural network:1||Spinorbit torque (SOT):1||accelerator:1||Monte Carlo:1||halfselect problem:1||hardware security:1||phase transition engineering:1||atomic layer deposition:1||implants:1||low power:1||Streaming:1||Overlapped message passing (OMP):1||Flexible circuit:1||NAND flash memory:1||impedance matching:1||impedance searching:1||Coordinate rotation digital computer (CORDIC):1||data priority:1||QR Decomposition:1||networkonchip:1||Embedded memory:1||Baseband modem:1||기븐스 회전:1||VPP generator:1||transparent:1||driving circuit:1||maximum likelihood demodulation:1||lowcomplexity chase (LCC):1||Inmemory computing (IMC):1||cache:1||Performance evaluation:1||MNIST:1||Spiketiming dependent plasticity:1||spinorbit torque magnetic tunnel junction based nonvolatile flipflops:1||stored data:1||backup energy:1||MTJbased NVFFs:1||0 nm:1||matrixvector multiplication:1||3D (3dimension) scanning:1||highthroughput digital signal processor:1||lowpower image processing:1||2T gain cell:1||logiccompatible eDRAM:1||Richardson method:1||Very large scale integration (VLSI) implementation:1||hybrid folded key equation solver (KES):1||spintransfer torque RAM (STTRAM):1||read stability:1||ultra lowpower:1||QRMMLD:1||serial access memory:1||Wireless communication:1||gain cell:1||Wearable computing:1||Quasicyclic (QC) codes:1||fieldprogrammable gate array (FPGA):1||discrete cosine transform (DCT):1||Givens Rotation:1||traffic permutation:1||Access pattern:1||SRAM bitcell:1||Active leakage energy:1||parallel architecture:1||ultra wideband (UWB):1||QR 분해:1||코딕:1||Approximate filtering:1||Lowpower very large scale integration (VLSI) design:1||Networkonchip:1||network nanotube:1||High Rate WPAN:1||latency:1||Adaptive sensing:1||memory cell structure:1||Throughput:1||VCMA effect:1||Sensors:1||Sensing circuit:1||temporal coding:1||Error compensation:1||Spiking neural network:1||System on a Chip:1||Membrane potentials:1||randomaccess storage:1||flipflops:1||stuck at fault:1||Dual laser profile:1||Deep neural network:1||low complexity:1||VLSI design:1||Error Correction Code (ECC):1||Robust Nanoscale Memory:1||Runtime Protection:1||yield:1||Massive MIMO:1||Reformulation:1||Channel matrix:1||capacitance equivalent oxide thickness:1||Error correction code (ECC):1||Security:1||wearables:1||Lowdensity parity check (LDPC) codes:1||Capacitor matrix:1||Embedded random access memory (RAM):1||energyefficiency:1||Embedded static random access memory (SRAM):1||Householder:1||Multimedia:1||networkonchip (NoC):1||ultrathin display:1||vectoring mode:1||lookahead:1||Very large scale integration (VLSI):1||Hardware architecture:1||softdecision decoding:1||Packet Buffering:1||Fairness:1||algebraic softdecision decoding (ASD):1||memory:1||computeinmemory (CIM):1||Spinorbit torque device:1||Logic gates:1||digital processing inmemory:1||Integrated circuit reliability:1||dynamic reference:1||Neuromorphic:1||deep neural network:1||spiking neural network processor:1||magnetoelectronics:1||powergating mode:1||data backup scheme:1||DFT:1||Vibration compensation:1||Convolutional neural networks:1||GramSchmidt:1||Memory Failures:1||capacitive coupling:1||chargerecycling:1||write ability:1||timetodigital converter (TDC):1||STTMRAM:1||Infraless communication:1||LDPC decoder:1||memorybased computing:1||error correction code (ECC):1||low voltage operation:1||softthreshold algorithm:1||wavelet ECG detector:1||Backtracking:1||wavepipeline:1||ultralow voltage:1||병렬 연산:1||Alldigital phaselocked loop (ADPLL):1||sign prediction:1||carbon nanotube:1||Timing phase:1||Congestion Control:1||WiMedia MAC:1||content addressable memory (CAM):1||Transistors:1||memory operation energy:1||Torque:1||Voltage:1||Neuromorphic system:1||Complexity theory:1||Onchip learning:1||lowpower electronics:1||magnetic tunnelling:1||zeroleakage standby state:1||size 65:1||Processinginmemory:1||parallelism:1||Laser profile:1||Laser profile scanner:1||Galoisfield (GF) arithmetic:1||fast fourier transform (FFT):1||write margin (WRM):1||Iterative signal detection:1||Associative computing:1||digital signal processor:1||variation:1||mesostructure:1||privacy:1||MIMO detection:1||Transition metal dichalcogenide:1||Molybdenum disulfide:1||Organic thinfilm transistor:1||peak current consumption:1||bit line:1||lowpower:1||Embedded SRAM:1||Low voltage operation:1||Implantable cardiac pacemaker:1||multiscaled product:1||dynamic pathsetup:1||reconfigurable design:1||capacitive touch sensor (CapTSP):1||jitter:1||matrix decomposition:1||multiinputmultioutput (MIMO) demodulation:1||Multirate system:1||Polyphase channelizer:1||Low power VLSI design:1||Deep neural network (DNN) accelerator:1||ReedSolomon (RS) codes:1||Metals:1||Reliability:1||Energyefficient neuromorphic system:1||

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