ScholarWorks@Korea University: Kim, Seon Wook

Detailed Information

Kim, Seon Wook (김선욱)

College of Engineering

Research Area

Tel 3251
Homepage

ResearcherID ORCiD Scopus Google Scholar ID ResearchGate

Keyword

DRAM:4||design optimization:2||epochbased execution:2||parallel simulation:2||inmemory processing:2||decoding:2||redundancy repair:2||DRAM fault recovery:2||HLLtoHDL translator:2||GDB:2||energy consumption:2||compiler:2||EISC architecture:2||USBJTAG:2||JavaScript:2||data dependency:1||visually lossless:1||universal hashing:1||parallelization:1||JIT:1||javascriptcore:1||javascript compilers:1||Wireless memory:1||Dalvik virtual machine:1||resource optimization:1||Memory Leakage:1||GNU 디버거:1||EISC 아키텍처:1||block interleaving:1||SilentPIM:1||packet alignment:1||Bfloat16:1||Switches:1||Random access memory:1||processinginDRAM:1||Multiplyaccumulate:1||DRAM refresh:1||video compression:1||EDP:1||encoding:1||Dynamic voltage scaling:1||SRAM reliability:1||cache replacement policy:1||delaylocked loop (DLL):1||distributed compiler:1||메모리 오류 검출 도구:1||ILP:1||TLP:1||MLEP:1||LSTM:1||Lookuptable:1||JEDEC:1||optimal scheduling:1||ASIC:1||DRAM verification:1||retention time:1||stuckat fault:1||RFID:1||Performance analysis:1||instrumentation:1||remote linking:1||multiband orthogonal frequencydivision multiplexing (MBOFDM):1||low power filter:1||FPGA:1||CPUFPGA cross call:1||MBOFDM:1||VerilogHDL:1||DMA:1||Activationfunctions:1||Deepneuralnetworks:1||Engines:1||Programming:1||direct memory access:1||ISAs:1||BISR algorithm:1||lifetime:1||bit flips:1||Bit shuffling:1||PCM:1||Streaming:1||Internet of Things:1||Android:1||Baseband modem:1||CPUFPGA communication interface:1||Flexibility:1||USBJTAG 인터페이스:1||Mixed Radix System (MRS):1||standard memory requests:1||a burst length:1||command scheduling:1||matrixvector multiplication:1||Pipelining:1||Advanced Encryption Standard (AES):1||Wireless communication:1||extendable instruction set computing (EISC):1||parallel architecture:1||ultra wideband (UWB):1||Approximate filtering:1||PDP:1||Decoupled Architecture:1||compiler framework:1||Registers:1||ProcessinginDRAM:1||PIMbased execution:1||computational graph:1||M3D stacking:1||TSVBased 3D stacking:1||register operand detection:1||cloud computing:1||power reduction:1||Matrixvector multiplication:1||javascript engines:1||VCCMIN:1||OpenCL:1||OpenCL to WebCL translation:1||hardware performance counter:1||dynamic frequency scaling (DFS):1||GCC2Verilog:1||Hardwaresoftware codesign:1||Timing Controller:1||Array processor:1||SMT:1||CMP:1||reconfigurable processor:1||Java:1||MIPI DSI:1||Computer architecture:1||instruction set architecture:1||test coverage:1||bit shifting:1||endurance:1||Performance:1||Infraless communication:1||WebCL:1||Calibration:1||Memorycomputation decoupling:1||allbank execution:1||DRAM chips:1||PIM offloading:1||test sequence:1||Display stream compression:1||microarchitecture simulation:1||Processinginmemory:1||parallelism:1||Architectural simulation:1||selective refresh:1||fault recovery algorithm:1||DRAM yield:1||memory system simulator:1||DRAMSim2:1||loop parallelization:1||HTML5:1||Reliability:1||reconfigurable design:1||Memory Error Detection Tool:1||메모리 누출:1||standard memory interface:1||a memory controller:1||profiling:1||

RSS_1.0 RSS_2.0 ATOM_1.0

145 Anam-ro, Seongbuk-gu, Seoul, 02841, Korea+82-2-3290-2963

Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.

Detailed Information

Keyword

BROWSE