ScholarWorks@Korea University: KIM, Chul woo

Detailed Information

KIM, Chul woo (김철우)

College of Engineering

Research Area

Tel 02-3290-3252
Homepage

ResearcherID ORCiD Scopus Google Scholar ID ResearchGate

Keyword

Clocks:14||Switches:10||receiver:9||Capacitors:9||Receivers:9||low power:8||maximum power point tracking (MPPT):8||Pins:6||Decoding:6||Delays:6||Random access memory:5||Timedomain analysis:5||Energy harvesting:5||Transistors:5||dcdc converter:5||Decision feedback equalizers:5||energy harvesting (EH):5||transceiver:4||delaylocked loop (DLL):4||Jitter:4||CMOS:4||energy harvesting:4||Timing:4||power management:4||Optical signal processing:4||memory interface:4||continuoustime linear equalizer (CTLE):4||Voltage:4||Bandwidth:4||Delay lines:3||Voltage control:3||Detectors:3||Decision feedback equalizer (DFE):3||Regulators:3||thermoelectric generator (TEG):3||Video recording:3||Generators:3||Maximum power point trackers:3||duty cycle corrector (DCC):3||Internet of Things:3||phaselocked loop (PLL):3||Adaptive equalizer:3||rectifier:3||PLL:3||dynamic random access memory (DRAM):3||subsampling:3||Calibration:3||DCDC converter:3||Clock and data recovery (CDR):3||Analogtodigital converter (ADC):3||DRAM:3||DisplayPort:2||lowdropout (LDO) regulator:2||variation:2||low jitter:2||selfcalibration:2||MOS devices:2||singleended interface:2||triboelectric nanogenerator (TENG):2||Capacitance:2||voltage 0:2||multilevel signaling:2||spreadspectrum clock generator (SSCG):2||DLL:2||Clock and data recovery:2||Bit error rate:2||Power conversion:2||Gain:2||timetodigital converter:2||EMI reduction:2||clock and data recovery (CDR):2||Frequencytodigital converter:2||Battery charger:2||1/f noise:2||Antiharmonic lock:2||Singleended receiver:2||decision feedback equalizer:2||periodic charge refresh:2||ADDLL:2||successive approximation register (SAR):2||solar cell:2||embedded clock:2||Adaptive equalizers:2||Topology:2||equalization:2||delaylocked loop:2||forward body biasing:2||DRAM interface:2||DDR3:2||decision feedback equalizer (DFE):2||Latches:2||Wireless communication:2||Analogtodigital conversion:2||Transceivers:2||Threshold voltage:2||Charge pumps:2||Circuits:2||highspeed memory interface:2||integrator:2||fully integrated voltage regulator:2||Computer architecture:2||networkonchip (NoC):2||decisionfeedback equalizer (DFE):2||highspeed integrated circuits:2||fast transient response:2||Batteries:2||Frequency conversion:2||Throughsilicon vias:2||Active inductor:2||referenceless:2||boost converter:2||timetodigital converter (TDC):2||PVT variation:2||temperature sensor:2||wireless sensor networks (WSNs):2||SAR ADC:2||Microprocessors:2||lowpower electronics:2||voltagecontrolled oscillators:2||clockembedded signaling (CES):2||Internet of Things (IoT):2||multiple outputs:1||pulse amplitude modulation (PAM3):1||phase interpolator:1||dynamic residue amplifier:1||Ultralow voltage:1||fractional opencircuit voltage (FOCV) method:1||digital phase locked loops:1||frequency 480:1||0 MHz:1||doubledie package (DDP):1||electrostatic discharge (ESD):1||transition density (TD):1||deemphasis:1||INWE:1||adaptive calibration:1||digital lowdropout (DLDO) regulator:1||dynamic voltage frequency scaling (DVFS):1||Clock and data recovery circuit (CDR):1||Adaptivebandwidth PLL:1||graphics DRAM interface:1||preand deemphasis:1||readout circuit:1||clock and data recovery circuits:1||phase locked loops:1||DAC:1||Wireless memory:1||lowvoltage differential signaling (LVDS):1||harmonic lock:1||power down exit time:1||wakeup time:1||Allcomparator control:1||oneshot pulse generator:1||thermoelectric energy harvesting:1||photovoltaic (PV):1||wireless sensor network (WSN):1||referenceless transceiver:1||CDR:1||wide tracking range:1||65 nm CMOS process:1||Guaranteed throughput:1||OADCC:1||frequencytovoltage converter (FVC):1||nonlinear profile:1||lifetime:1||widerange:1||CMOS smart sensor:1||frequency multiplication:1||limited locking range:1||Electromagnetic interference (EMI):1||block interleaving:1||Clock generator:1||Delaylocked loop (DLL):1||fine code generator:1||fast lock time:1||spike:1||dualmode operation:1||Transmitters:1||transmitter:1||Bitefficient signaling:1||multiwire signaling:1||charge redistribution:1||chargesteering logic:1||ring oscillator:1||switched capacitor (SC):1||timedomain decision technique:1||Simulation:1||wireless sensor node (WSN):1||switchedcapacitor LDO (SCLDO):1||singleended signaling:1||Power system measurements:1||Miller compensation:1||linear search:1||lowdropout regulator (LDO):1||doubleconversion rejection technique (DCRT):1||multiple inputs:1||openloop:1||Analogdigital conversion:1||linearity:1||nearthreshold voltage:1||DCDC power conversion:1||CMOS digital integrated circuits:1||augmented reality:1||digital phaselocked loop:1||charger:1||redistribution layer (RDL):1||Energy harvesting (EH):1||ripple correlation control (RCC):1||spreadspectrum clock:1||Liion battery:1||Spread spectrum clock:1||EDP:1||crosstalkinduced jitter (CIJ) reduction:1||intersymbol interference (ISI) reduction:1||sensitivity analysis:1||complementary metal oxide semiconductor:1||digitalanalog converter:1||18 mum:1||5 V to 1:1||calibration:1||input folding:1||piezoelectric:1||energy efficient:1||pulse oximeter:1||charge pump:1||Output driver:1||Datadependent jitter:1||voltage doubler:1||DDR2:1||GDDR3:1||halfclock phase inverting:1||variable delay line:1||Electromagnetic interference (EMI) reduction:1||leakage power:1||selfaligner:1||oversampling:1||pingpong delay line:1||multistage interconnection network:1||permutation network:1||pipelined circuitswitching:1||guaranteed throughput:1||onchip switch:1||voltagetotime converter:1||Column address strobe (CAS) latency controller:1||DRAMs:1||switched biasing amplifier:1||frequency modulation:1||Adaptive bandwidth delaylocked loop(DLL):1||adaptive clock gating:1||false lock:1||range doubler:1||spin Hall effect:1||twodimensional electron gas:1||ILP:1||TLP:1||MLEP:1||hybrid buckboost converter:1||dualinput dualoutput:1||chopping technique:1||CT Delta Sigma M:1||Cascade delaylocked loop:1||Interpolation:1||cycle successive approximation register (SAR) analogtodigital converter (ADC):1||feedforward equalizer (FFE):1||multichip module (MCM):1||Monitoring:1||differential mode (DM):1||Stability criteria:1||Analog frontend (AFE):1||duobinary:1||Process control:1||double data rate (DDR):1||Buck converter:1||Temperature measurement:1||Capacitively coupled level shifter (LS):1||Prototypes:1||switching algorithm:1||Capacitively coupled level shifter (CCLS):1||Buck converters:1||timedigital conversion:1||55 V:1||dataembedded clock signaling:1||Chargeddevice model (CDM):1||columnselection line (CSL) transistor:1||photovoltaic (PV) cells:1||wireless interference:1||EMI:1||AC termination:1||Memory:1||singleended global I/O:1||VCO calibration:1||Bit error rate (BER):1||jitter tolerance (JTOL):1||receiver (Rx):1||ground noise sensitivity:1||RtoR regulating VCO:1||multiplephase clock:1||display driver IC:1||1P6M CMOS technology:1||RFID:1||spinFET:1||ubiquitous healthcare (uhealthcare):1||low voltage:1||wide range:1||multiple output:1||registercontrolled DLL:1||singleinductor multioutput (SIMO) DCDC converter:1||piecewise linear approximation:1||data confliction:1||synchronous mirror delay (SMD):1||circuitswitched:1||source synchronous:1||flash converter:1||successive approximation register (SAR) controller:1||IDD3P:1||NewtonRaphson modulation profile:1||DDR2 SDRAM:1||photovoltaic (PV) systems:1||semidigital dualloop:1||linear PD:1||lowjitter:1||onchip router:1||data permutation:1||slew rate:1||MBOFDM:1||lock time:1||oscillator and ramp generator:1||Pd/CoFe multilayer:1||Pulse generation:1||rms inductor current reduction:1||sensor readout IC:1||wireline interface:1||selferror corrector (SEC):1||Quantization (signal):1||intersymbol interference (ISI):1||analog equalizer:1||Charge pump:1||selfgenerated offset calibration:1||Dynamic voltage and frequency scaling (DVFS):1||Lowpower energy harvesting:1||maximum power point trackers (MPPT):1||timebased (TB) MPPT:1||Signal to noise ratio:1||Memory interface:1||Power demand:1||Logic:1||highvoltage (HV) sampling:1||inductor sharing:1||Leakage currents:1||MDLL:1||solar energy:1||AR display system:1||NTV region:1||power dissipation:1||lowsupply voltage:1||dynamic voltage range:1||augmented reality display system:1||near threshold voltage digital PLL:1||current 160:1||Inductance:1||parasitic inductance:1||sense amplifier:1||fully integrated:1||SSCG:1||RSCE:1||fasttransientresponse time:1||training sequence:1||Correlated double sampling:1||touch panel:1||driver circuits:1||railtorail regulating voltagecontrolled oscillator:1||phase locked loop:1||size 0:1||8 V:1||voltage 18 V:1||frequency 140 MHz to 240 MHz:1||2 V:1||Streaming:1||onecycle sensing:1||conversion efficiency:1||preemphasis:1||Highspeed serial link:1||Comparator:1||ACDC converter:1||Compensation:1||process variation compensation:1||spread spectrum clock generation (SSCG):1||deep power down:1||through silicon via (TSV):1||phase and frequency detection:1||networkonchip:1||Double data rate (DDR):1||merged dual coarse delay line (MDCDL):1||ORAND DCC:1||consumer DRAMs:1||dynamic voltage scaling (DVS):1||solar energy harvesting:1||vernier phase shifter:1||Opampsharing:1||V/I converter:1||fast compensation:1||voltage:1||Mixed Radix System (MRS):1||duty detector:1||multiphase clock generator:1||Circuits and systems:1||Continuous output delivery current:1||DCDC power converters:1||analogtodigital converter (ADC):1||ripple:1||Nonlinear distortion:1||dynamic randomaccess memory:1||2bit:1||flipflop:1||DCbalanced signaling:1||pulse amplitude modulation (PAM):1||selfreferenced:1||differential signaling:1||channel attenuation:1||Fourlevel pulseamplitude modulation (PAM4):1||timewindowed least significant bit (LSB) decoder:1||Transconductance:1||wireline transceiver:1||Highpass filter:1||Circuit stability:1||time domain:1||throughsilicon via (TSV) I/O:1||Wireless sensor networks:1||dc&#8211:1||dual input (DI):1||MPCG:1||QDR:1||Registers:1||intersignal skew compensation:1||SAR:1||Linearity:1||fully dynamic pipelined analogtodigital converter (ADC):1||Nanogenerators:1||timing jitter:1||0 nm:1||graphics DRAM:1||Integrated circuit modeling:1||intrapanel interface (IPI):1||fuel gauge:1||state of charge (SOC):1||wireless sensor node:1||inter symbol interference:1||CMOS integrated circuit:1||subsampling phaselocked loop (SSPLL):1||Receiver (Rx):1||adaptive equalizer (EQ):1||edgepursuit comparator (EPC):1||oscillator collapse:1||channel mismatch:1||deskew algorithm:1||multichannel interface:1||timeinterleaving (TI):1||maximum power point:1||FET logic devices:1||threshold voltage:1||bandwidth (BW) control:1||DDR1:1||tDQSCK:1||Alldigital PLL (ADPLL):1||delaycellless TDC:1||low noise VCO:1||crossregulation:1||hysteresis comparator:1||Alldigital phaselocked loop:1||jitter reduction:1||power down:1||selfrefresh:1||extendable instruction set computing (EISC):1||Coarse grained array (CGA):1||traffic permutation:1||timedomain comparison:1||dual coarse delay line:1||lowpower design:1||process variationaware design:1||charge pump (CP):1||pipelined analogtodigital converter (ADC):1||Temperature sensor:1||Networkonchip:1||duty cycle correction:1||digital clock generator:1||quadrature phase clock generator:1||Power generation:1||RRL:1||Ethernet applications:1||jitter tolerance:1||direct inputoutput phase comparison:1||Frequency response:1||Phase noise:1||quantization noise (Qnose):1||Pulse amplitude modulation4 (PAM4):1||Sensors:1||Common mode (CM):1||Dataedge sampling:1||MOSFET:1||fully dynamic ADC:1||zoom ADC:1||Highbandwidth memory (HBM):1||receiver (RX):1||Transient analysis:1||Load modeling:1||conditional switching signal:1||perpin skew:1||bitdeskew:1||digital lowdropout (DLDO) regulator:1||sigmadelta modulation:1||ultralow power consumption:1||low voltage optimised digitally controlled oscillator:1||CMOS technology:1||Adaptive input ripple (AIR):1||Electrostatic discharges:1||gate oxide breakdown:1||singledie package (SDP):1||very fast transmissionline pulse (VFTLP):1||receiver margin:1||Battery:1||SOC indicator:1||I/O:1||nearground signaling (NGS):1||IIR filter:1||onchip signaling:1||frequency detector:1||Commonmode CDAC:1||highresolution ADC:1||phase domain:1||fast precharging sampler (FPsampler):1||incell:1||timeinterleaved analogtodigital converters (TIADCs) calibration:1||CMOS integrated circuits:1||digitalanalogue conversion:1||clock and data recovery:1||flatpanel display interface:1||spinpolarized transport:1||Body biasing:1||transmitter (TX):1||comparator sharing technique:1||timelimited power distribution control (TPDC):1||pixel clock generation:1||half period detector:1||short current:1||dynamic frequency scaling (DFS):1||magnetic Hall sensor:1||frequencylocked loop (FLL):1||onchip:1||output enable control:1||selfreconfigurable design:1||switched bias:1||low voltage differential signaling (LVDS):1||Ring oscillator:1||Array processor:1||clockondemand:1||portable:1||frequency multiplier:1||pulsewidthmodulation (PWM):1||SMT:1||CMP:1||augmented reality microdisplay:1||counterbased adaptive equalizer:1||zerocurrent detector (ZCD):1||Continuously scalableconversionratio (CSCR):1||dcdc converter:1||Adaptive threshold voltage calibration:1||highspeed interface:1||Asymmetric interface:1||symbol correlation:1||Highspeed link:1||receivers:1||Ring oscillators:1||dualdomain phase detector (DDPD):1||LSB decoding method:1||Logic gates:1||pulse amplitude modulation 4 (PAM4):1||Conversionratio modulation (CRM):1||Noise:1||Transient response:1||digital lowdropout regulator (DLDO):1||dc converter:1||nonperiodic signal:1||openloop amplifier:1||maximum power point (MPP) analysis:1||digital analogue blocks:1||0 muA:1||Graphics processing units:1||clock extraction:1||ondie termination:1||energy efficiency:1||lowpower DRAM:1||DFE:1||Autocalibration:1||compliance test:1||clock frequency multiplier:1||referenceless frequency acquisition circuit (RFAC):1||Data encryption:1||true random number generator (TRNG):1||noise reduction:1||frequency detection:1||referenceless receiver:1||realtime jitter tolerance enhancer (JTE):1||interface block:1||size 1:1||6 mum:1||resistive digitaltoanalog converter (RDAC):1||Infraless communication:1||ramp generator:1||Preemphasis:1||piezoelectric (PE):1||switchedcapacitor (SC):1||vibration energy harvesting:1||frequencytodigital converter:1||oscillator:1||thermal energy harvesting:1||GDDR6:1||phase detection:1||voltage regulator:1||Backtracking:1||wavepipeline:1||dutycycle corrector (DCC):1||IDD3N:1||All digital gates:1||optimum power point tracking (OPPT):1||widerange CDR:1||process:1||double date rate:1||Digital delaylocked loop (DDLL):1||liquid crystal on silicon (LCoS):1||Inductors:1||multiphase dcdc converter:1||CCIA:1||chopping artifacts:1||noisefolding:1||phase rotator:1||dynamic randomaccess memory (DRAM):1||equalizer (EQ):1||Feedforward systems:1||Phase locked loops:1||Digital phaselocked loop (PLL):1||load transient response:1||pulse amplitude modulation (PAM)3:1||least significant bit (LSB) decoding method:1||signaling:1||Density measurement:1||Threedimensional displays:1||Buckbased dualconversion (BBDC):1||threelevel gate driver (TLGD):1||multiphase clock generator:1||subrange:1||Electrodes:1||optimised power efficiency:1||DPLL:1||sigmadelta modulator block:1||jitter characteristic:1||size 65:1||Graphics:1||referenceless interface:1||coupling capacitance:1||Braid clock signaling (BCS):1||electromagnetic interference (EMI):1||digital compensation:1||nested modulation profile:1||display interface:1||postLPDDR4:1||near threshold voltage:1||digital cell library:1||LPDDR:1||synchronous dynamic random access memory (SDRAM):1||single loop:1||noise analysis:1||National Institute of Standards and Technology (NIST) test:1||selfcapacitance:1||bandwidth mismatch:1||DDI:1||voltage 1:1||magnetoresistance:1||deadtime:1||Analog delaylocked loop (DLL):1||digital DLL:1||halfclock phase control:1||lock range:1||temperature variation:1||infinite phase shift:1||onchip communication network:1||reconfigurable computing:1||dynamic pathsetup:1||Analogtodigital converter:1||dynamic offset cancellation:1||Double binaryweighted DAC:1||current source:1||process, supply voltage, and temperature (PVT) detector:1||adaptive design technique:1||frequencyaware design:1||Temperature compensation:1||and temperature (PVT) variation detection:1||timebased receiver:1||pulse amplitude modulation4 (PAM4):1||highspeed SAR ADC:1||interpolation technique:1||Impedance:1||transition density:1||Receiver (RX):1||nonreturntozero (NRZ):1||Attenuation:1||jitter:1||lowpower:1||singleended:1||time quantizer:1||Oscillators:1||Symbols:1||nonreturn to zero (NRZ):1||reconfigurable converter:1||switchedcapacitor converter:1||voltage conversion ratio (VCR):1||dynamic amplifier:1||floating inverter amplifier:1||Energy efficiency:1||halfbaudrate:1||sense amplifier (SA):1||Binary search:1||

RSS_1.0 RSS_2.0 ATOM_1.0

145 Anam-ro, Seongbuk-gu, Seoul, 02841, Korea+82-2-3290-2963

Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.

Detailed Information

Keyword

BROWSE