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Early wakeup: improving the drowsy cache performance

Authors
Shim, SunghoonChung, SungwooChoi, HongjunKim, Cheol Hong
Issue Date
2014
Publisher
TUBITAK SCIENTIFIC & TECHNICAL RESEARCH COUNCIL TURKEY
Keywords
Processor architecture; low-power design; leakage power; drowsy cache; early wakeup
Citation
TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES, v.22, no.2, pp.425 - 433
Indexed
SCIE
SCOPUS
Journal Title
TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES
Volume
22
Number
2
Start Page
425
End Page
433
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/101167
DOI
10.3906/elk-1201-90
ISSN
1300-0632
Abstract
As process technology scales down, leakage power consumption becomes comparable to dynamic power consumption. The drowsy cache technique is known as one of the most popular techniques for reducing the leakage power consumption in the data cache. However, the drowsy cache is reported to degrade the processor performance significantly. In this paper, to maintain the performance of the processor with the drowsy cache technique, we propose an early wakeup technique, which predicts the next cache line to be requested by utilizing the way-prediction information. The proposed technique efficiently reduces the number of accesses to the cache lines in drowsy mode. Our simulation results show that the proposed technique reduces the extra delay due to the drowsy cache scheme by 29.6%, on average.
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