A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC
DC Field | Value | Language |
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dc.contributor.author | Song, Minyoung | - |
dc.contributor.author | Jung, Inhwa | - |
dc.contributor.author | Pamarti, Sudhakar | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-05T18:13:48Z | - |
dc.date.available | 2021-09-05T18:13:48Z | - |
dc.date.created | 2021-06-15 | - |
dc.date.issued | 2013-12 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/101378 | - |
dc.description.abstract | An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-mu m CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 mm(2) consumes 12 mA and its measured jitter is 4 ps(rms) at 2.4 GHz. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | RING OSCILLATOR | - |
dc.subject | LOW-NOISE | - |
dc.subject | CONVERTER | - |
dc.subject | PLL | - |
dc.title | A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/TCSI.2013.2265975 | - |
dc.identifier.scopusid | 2-s2.0-84890075991 | - |
dc.identifier.wosid | 000327724900007 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.60, no.12, pp.3145 - 3151 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.citation.volume | 60 | - |
dc.citation.number | 12 | - |
dc.citation.startPage | 3145 | - |
dc.citation.endPage | 3151 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | RING OSCILLATOR | - |
dc.subject.keywordPlus | LOW-NOISE | - |
dc.subject.keywordPlus | CONVERTER | - |
dc.subject.keywordPlus | PLL | - |
dc.subject.keywordAuthor | All-digital PLL (ADPLL) | - |
dc.subject.keywordAuthor | delay-cell-less TDC | - |
dc.subject.keywordAuthor | low noise VCO | - |
dc.subject.keywordAuthor | phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | time-to-digital converter (TDC) | - |
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