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Back biasing effects in tri-gate junctionless transistors
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Park, So Jeong | - |
| dc.contributor.author | Jeon, Dae-Young | - |
| dc.contributor.author | Montes, Laurent | - |
| dc.contributor.author | Barraud, Sylvain | - |
| dc.contributor.author | Kim, Gyu-Tae | - |
| dc.contributor.author | Ghibaudo, Gerard | - |
| dc.date.accessioned | 2021-09-05T22:12:50Z | - |
| dc.date.available | 2021-09-05T22:12:50Z | - |
| dc.date.created | 2021-06-14 | - |
| dc.date.issued | 2013-09 | - |
| dc.identifier.issn | 0038-1101 | - |
| dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/102305 | - |
| dc.description.abstract | The back bias effect on tri-gate junctionless transistors (JLTs) has been investigated using experimental results and 2-D numerical simulations, compared to inversion-mode (IM) transistors. Results show that JLT devices are more sensitive to back biasing due to the bulk conduction. It is also shown that the effective mobility of JLT is significantly enhanced below flat band voltage by back bias. However, in extremely narrow JLTs, the back bias effect is suppressed by reduced portion of bulk conduction and strong sidewall gate controls. 2-D numerical charge simulation well supports experimental results by reconstructing the trend of back bias effects. (c) 2013 Elsevier Ltd. All rights reserved. | - |
| dc.language | English | - |
| dc.language.iso | en | - |
| dc.publisher | PERGAMON-ELSEVIER SCIENCE LTD | - |
| dc.subject | ELECTRICAL CHARACTERISTICS | - |
| dc.subject | NANOWIRE MOSFET | - |
| dc.subject | MOBILITY | - |
| dc.title | Back biasing effects in tri-gate junctionless transistors | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Kim, Gyu-Tae | - |
| dc.identifier.doi | 10.1016/j.sse.2013.06.004 | - |
| dc.identifier.scopusid | 2-s2.0-84879809146 | - |
| dc.identifier.wosid | 000322942200013 | - |
| dc.identifier.bibliographicCitation | SOLID-STATE ELECTRONICS, v.87, pp.74 - 79 | - |
| dc.relation.isPartOf | SOLID-STATE ELECTRONICS | - |
| dc.citation.title | SOLID-STATE ELECTRONICS | - |
| dc.citation.volume | 87 | - |
| dc.citation.startPage | 74 | - |
| dc.citation.endPage | 79 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Article | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalResearchArea | Physics | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
| dc.relation.journalWebOfScienceCategory | Physics, Condensed Matter | - |
| dc.subject.keywordPlus | ELECTRICAL CHARACTERISTICS | - |
| dc.subject.keywordPlus | NANOWIRE MOSFET | - |
| dc.subject.keywordPlus | MOBILITY | - |
| dc.subject.keywordAuthor | SOI (silicon on insulator) | - |
| dc.subject.keywordAuthor | Junctionless transistor | - |
| dc.subject.keywordAuthor | Back bias effect | - |
| dc.subject.keywordAuthor | Channel width variation | - |
| dc.subject.keywordAuthor | 2-D numerical simulation | - |
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