A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hwang, Sewook | - |
dc.contributor.author | Kim, Kyeong-Min | - |
dc.contributor.author | Kim, Jungmoon | - |
dc.contributor.author | Kim, Seon Wook | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-06T03:51:48Z | - |
dc.date.available | 2021-09-06T03:51:48Z | - |
dc.date.created | 2021-06-14 | - |
dc.date.issued | 2013-03 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/103823 | - |
dc.description.abstract | This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of 0.5 to 8 of the reference clock, according to the workload of the EISC processor. The proposed analog self-calibration method and a phase detector with an auxiliary charge pump can effectively reduce the delay mismatch between delay cells in the voltage-controlled delay line and the static phase offset due to the current mismatch in the charge pump, respectively. The self-calibrated output waveform exhibits 9.7 ps of RMS jitter and 73.7 ps of peak-to-peak jitter at 120 MHz. The prototype clock generator implemented in a 0.18-m CMOS process occupies an active area of 0.27 mm and consumes 15.56 mA. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | FREQUENCY-MULTIPLIER | - |
dc.subject | DYNAMIC VOLTAGE | - |
dc.subject | LOCKED LOOP | - |
dc.subject | COMPENSATION | - |
dc.subject | CMOS | - |
dc.title | A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Seon Wook | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/TVLSI.2012.2188656 | - |
dc.identifier.scopusid | 2-s2.0-84874647018 | - |
dc.identifier.wosid | 000315639900018 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.21, no.3, pp.575 - 579 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 21 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 575 | - |
dc.citation.endPage | 579 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | FREQUENCY-MULTIPLIER | - |
dc.subject.keywordPlus | DYNAMIC VOLTAGE | - |
dc.subject.keywordPlus | LOCKED LOOP | - |
dc.subject.keywordPlus | COMPENSATION | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordAuthor | Calibration | - |
dc.subject.keywordAuthor | dynamic frequency scaling (DFS) | - |
dc.subject.keywordAuthor | delay-locked loop (DLL) | - |
dc.subject.keywordAuthor | extendable instruction set computing (EISC) | - |
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