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Effects of channel width variation on electrical characteristics of tri-gate Junction less transistors

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dc.contributor.authorJeon, Dae-Young-
dc.contributor.authorPark, So Jeong-
dc.contributor.authorMouis, Mireille-
dc.contributor.authorBarraud, Sylvain-
dc.contributor.authorKim, Gyu-Tae-
dc.contributor.authorGhibaudo, Gerard-
dc.date.accessioned2021-09-06T03:57:52Z-
dc.date.available2021-09-06T03:57:52Z-
dc.date.created2021-06-14-
dc.date.issued2013-03-
dc.identifier.issn0038-1101-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/103859-
dc.description.abstractThe electrical behavior of tri-gate Junctionless transistors (JLTs) depending on top-effective width (W-top_eff) was investigated, experimentally. As decreasing W-top_eff, the amount of bulk neutral channel is relatively getting smaller than that of surface accumulation channel, whereas the channel sidewall gate effect is reinforced. These cause the shrinkage of the shoulder shape on the gate-to-channel capacitance characteristics (C-gc-V-g), resulting in a noticeable change in the effective mobility (mu(eff)) behavior from that in wide JLT devices, an increase of the threshold voltage (V-th), while the flat-band voltage (V-fb) does not change. 2D numerical simulation results, well consistent to the experimental results, confirm the significant sidewall gate effect in the tri-gate JLT devices with a narrow structure. (C) 2013 Elsevier Ltd. All rights reserved.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherPERGAMON-ELSEVIER SCIENCE LTD-
dc.subjectNANOWIRE TRANSISTORS-
dc.titleEffects of channel width variation on electrical characteristics of tri-gate Junction less transistors-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Gyu-Tae-
dc.identifier.doi10.1016/j.sse.2013.01.002-
dc.identifier.scopusid2-s2.0-84874701134-
dc.identifier.wosid000317444400011-
dc.identifier.bibliographicCitationSOLID-STATE ELECTRONICS, v.81, pp.58 - 62-
dc.relation.isPartOfSOLID-STATE ELECTRONICS-
dc.citation.titleSOLID-STATE ELECTRONICS-
dc.citation.volume81-
dc.citation.startPage58-
dc.citation.endPage62-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.relation.journalWebOfScienceCategoryPhysics, Condensed Matter-
dc.subject.keywordPlusNANOWIRE TRANSISTORS-
dc.subject.keywordAuthorJunctionless transistors (JLTs)-
dc.subject.keywordAuthorSidewall gate effect-
dc.subject.keywordAuthorEffective width-
dc.subject.keywordAuthorThreshold voltage (V-th)-
dc.subject.keywordAuthorFlat-band voltage (V-fb)-
dc.subject.keywordAuthorEffective mobility (mu(eff))-
dc.subject.keywordAuthor2D numerical simulation-
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