Effects of channel width variation on electrical characteristics of tri-gate Junction less transistors
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jeon, Dae-Young | - |
dc.contributor.author | Park, So Jeong | - |
dc.contributor.author | Mouis, Mireille | - |
dc.contributor.author | Barraud, Sylvain | - |
dc.contributor.author | Kim, Gyu-Tae | - |
dc.contributor.author | Ghibaudo, Gerard | - |
dc.date.accessioned | 2021-09-06T03:57:52Z | - |
dc.date.available | 2021-09-06T03:57:52Z | - |
dc.date.created | 2021-06-14 | - |
dc.date.issued | 2013-03 | - |
dc.identifier.issn | 0038-1101 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/103859 | - |
dc.description.abstract | The electrical behavior of tri-gate Junctionless transistors (JLTs) depending on top-effective width (W-top_eff) was investigated, experimentally. As decreasing W-top_eff, the amount of bulk neutral channel is relatively getting smaller than that of surface accumulation channel, whereas the channel sidewall gate effect is reinforced. These cause the shrinkage of the shoulder shape on the gate-to-channel capacitance characteristics (C-gc-V-g), resulting in a noticeable change in the effective mobility (mu(eff)) behavior from that in wide JLT devices, an increase of the threshold voltage (V-th), while the flat-band voltage (V-fb) does not change. 2D numerical simulation results, well consistent to the experimental results, confirm the significant sidewall gate effect in the tri-gate JLT devices with a narrow structure. (C) 2013 Elsevier Ltd. All rights reserved. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | PERGAMON-ELSEVIER SCIENCE LTD | - |
dc.subject | NANOWIRE TRANSISTORS | - |
dc.title | Effects of channel width variation on electrical characteristics of tri-gate Junction less transistors | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Gyu-Tae | - |
dc.identifier.doi | 10.1016/j.sse.2013.01.002 | - |
dc.identifier.scopusid | 2-s2.0-84874701134 | - |
dc.identifier.wosid | 000317444400011 | - |
dc.identifier.bibliographicCitation | SOLID-STATE ELECTRONICS, v.81, pp.58 - 62 | - |
dc.relation.isPartOf | SOLID-STATE ELECTRONICS | - |
dc.citation.title | SOLID-STATE ELECTRONICS | - |
dc.citation.volume | 81 | - |
dc.citation.startPage | 58 | - |
dc.citation.endPage | 62 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.relation.journalWebOfScienceCategory | Physics, Condensed Matter | - |
dc.subject.keywordPlus | NANOWIRE TRANSISTORS | - |
dc.subject.keywordAuthor | Junctionless transistors (JLTs) | - |
dc.subject.keywordAuthor | Sidewall gate effect | - |
dc.subject.keywordAuthor | Effective width | - |
dc.subject.keywordAuthor | Threshold voltage (V-th) | - |
dc.subject.keywordAuthor | Flat-band voltage (V-fb) | - |
dc.subject.keywordAuthor | Effective mobility (mu(eff)) | - |
dc.subject.keywordAuthor | 2D numerical simulation | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
(02841) 서울특별시 성북구 안암로 14502-3290-1114
COPYRIGHT © 2021 Korea University. All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.