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Low-power, wide-range time-to-digital converter for all digital phase-locked loops
- Authors
- Jeong, C. -H.; Kwon, C. -K.; Kim, H.; Hwang, I. -C.; Kim, S. -W.
- Issue Date
- 17-1월-2013
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Citation
- ELECTRONICS LETTERS, v.49, no.2, pp.96 - 97
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 49
- Number
- 2
- Start Page
- 96
- End Page
- 97
- ISSN
- 0013-5194
- Abstract
- A time-to-digital converter (TDC) for a low-power, wide-range all digital phase-locked loop (ADPLL) is presented. The proposed TDC uses an enabling signal with variable duration to achieve low power and wide range. For verification purpose, the ADPLL is fabricated in a 0.11 mu m CMOS technology. The ADPLL dissipates 6.02mW at an output frequency of 1.68GHz and its output frequency is measured as 0.24-1.68 GHz from a 1.2 V supply.
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