An On-Chip Network Fabric Supporting Coarse-Grained Processor Array
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Phi-Hung Pham | - |
dc.contributor.author | Phuong Mau | - |
dc.contributor.author | Kim, Jungmoon | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-06T05:39:30Z | - |
dc.date.available | 2021-09-06T05:39:30Z | - |
dc.date.created | 2021-06-14 | - |
dc.date.issued | 2013-01 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/104299 | - |
dc.description.abstract | Coarse grained arrays (CGAs) with run-time reconfigurability play an important role in accelerating reconfigurable computing applications. It is challenging to design on-chip communication networks (OCNs) for such CGAs with dynamic run-time reconfigurability whilst satisfying the tight budgets of power and area for an embedded system. This paper presents a silicon-proven design of a 64-PE circuit-switched OCN fabric with a dynamic path-setup scheme capable of supporting an embedded coarse-grained processor array. A proof-of-concept test chip fabricated in a 0.13 mu m CMOS process occupies a silicon area of 23 mm(2) and consumes a peak power of 200 mW @ 128 MHz and 1.2 Vcc, at room temperature. The OCN overhead consumes 9.4% of the area and 18% of the power of the total chip. Experimental results and analysis show that the proposed OCN fabric with its dynamic path-setup is suitable for use in an embedded CGA supporting fast run-time reconfigurability. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | An On-Chip Network Fabric Supporting Coarse-Grained Processor Array | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/TVLSI.2011.2181546 | - |
dc.identifier.scopusid | 2-s2.0-84871788554 | - |
dc.identifier.wosid | 000312835000022 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.21, no.1, pp.178 - 182 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 21 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 178 | - |
dc.citation.endPage | 182 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | Coarse grained array (CGA) | - |
dc.subject.keywordAuthor | network-on-chip (NoC) | - |
dc.subject.keywordAuthor | on-chip communication network | - |
dc.subject.keywordAuthor | reconfigurable computing | - |
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