An On-Chip Network Fabric Supporting Coarse-Grained Processor Array
- Authors
- Phi-Hung Pham; Phuong Mau; Kim, Jungmoon; Kim, Chulwoo
- Issue Date
- 1월-2013
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Coarse grained array (CGA); network-on-chip (NoC); on-chip communication network; reconfigurable computing
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.21, no.1, pp.178 - 182
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 21
- Number
- 1
- Start Page
- 178
- End Page
- 182
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/104299
- DOI
- 10.1109/TVLSI.2011.2181546
- ISSN
- 1063-8210
- Abstract
- Coarse grained arrays (CGAs) with run-time reconfigurability play an important role in accelerating reconfigurable computing applications. It is challenging to design on-chip communication networks (OCNs) for such CGAs with dynamic run-time reconfigurability whilst satisfying the tight budgets of power and area for an embedded system. This paper presents a silicon-proven design of a 64-PE circuit-switched OCN fabric with a dynamic path-setup scheme capable of supporting an embedded coarse-grained processor array. A proof-of-concept test chip fabricated in a 0.13 mu m CMOS process occupies a silicon area of 23 mm(2) and consumes a peak power of 200 mW @ 128 MHz and 1.2 Vcc, at room temperature. The OCN overhead consumes 9.4% of the area and 18% of the power of the total chip. Experimental results and analysis show that the proposed OCN fabric with its dynamic path-setup is suitable for use in an embedded CGA supporting fast run-time reconfigurability.
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