Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip
- Authors
- Phi-Hung Pham; Song, Junyoung; Park, Jongsun; Kim, Chulwoo
- Issue Date
- 1월-2013
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Guaranteed throughput; multistage interconnection network; network-on-chip; permutation network; pipelined circuit-switching; traffic permutation
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.21, no.1, pp.173 - 177
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 21
- Number
- 1
- Start Page
- 173
- End Page
- 177
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/104369
- DOI
- 10.1109/TVLSI.2011.2181545
- ISSN
- 1063-8210
- Abstract
- This paper presents the silicon-proven design of a novel on-chip network to support guaranteed traffic permutation in multiprocessor system-on-chip applications. The proposed network employs a pipelined circuit-switching approach combined with a dynamic path-setup scheme under a multistage network topology. The dynamic path-setup scheme enables runtime path arrangement for arbitrary traffic permutations. The circuit-switching approach offers a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks. A 0.13-mu m CMOS test-chip validates the feasibility and efficiency of the proposed design. Experimental results show that the proposed on-chip network achieves 1.9x to 8.2x reduction of silicon overhead compared to other design approaches.
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