Investigation of vertically trapped charge locations in Cr-doped-SrTiO3-based charge trapping memory devices
DC Field | Value | Language |
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dc.contributor.author | Seo, Yujeong | - |
dc.contributor.author | Song, Min Yeong | - |
dc.contributor.author | An, Ho-Myoung | - |
dc.contributor.author | Kim, Yeon Soo | - |
dc.contributor.author | Park, Bae Ho | - |
dc.contributor.author | Kim, Tae Geun | - |
dc.date.accessioned | 2021-09-06T14:43:11Z | - |
dc.date.available | 2021-09-06T14:43:11Z | - |
dc.date.created | 2021-06-15 | - |
dc.date.issued | 2012-10-01 | - |
dc.identifier.issn | 0021-8979 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/107238 | - |
dc.description.abstract | In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO3/Si3N4 interface to the bulk region of Si3N4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO3/Si3N4 interface by hole injection from the Si substrate into the Si3N4 layer at a high electric field (E-OX > 7 MV/cm). In addition, some of these charges passing across the SiO2 (OX) layer generate many Si-SiO2 interface traps (D-it: 1.58 x 10(12) cm(-2) eV(-1)) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick (> 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4757413] | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | AMER INST PHYSICS | - |
dc.subject | TRANSIENT ANALYSIS METHOD | - |
dc.subject | CHARACTERIZE | - |
dc.subject | STATES | - |
dc.title | Investigation of vertically trapped charge locations in Cr-doped-SrTiO3-based charge trapping memory devices | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Tae Geun | - |
dc.identifier.doi | 10.1063/1.4757413 | - |
dc.identifier.scopusid | 2-s2.0-84867504513 | - |
dc.identifier.wosid | 000310489400144 | - |
dc.identifier.bibliographicCitation | JOURNAL OF APPLIED PHYSICS, v.112, no.7 | - |
dc.relation.isPartOf | JOURNAL OF APPLIED PHYSICS | - |
dc.citation.title | JOURNAL OF APPLIED PHYSICS | - |
dc.citation.volume | 112 | - |
dc.citation.number | 7 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | TRANSIENT ANALYSIS METHOD | - |
dc.subject.keywordPlus | CHARACTERIZE | - |
dc.subject.keywordPlus | STATES | - |
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