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Analysis of electrical parameters of p-channel silicon nanowire transistors with selectively thinned channels on plastics

Authors
Lee, M.Jeon, Y.Kim, S.
Issue Date
27-8월-2012
Publisher
AMER INST PHYSICS
Citation
APPLIED PHYSICS LETTERS, v.101, no.9
Indexed
SCIE
SCOPUS
Journal Title
APPLIED PHYSICS LETTERS
Volume
101
Number
9
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/107678
DOI
10.1063/1.4747812
ISSN
0003-6951
Abstract
We present a technique for thinning the channel region of silicon nanowires (SiNWs) selectively while maintaining a thickness of the source/drain (S/D) regions in an attempt to minimize the parasitic series resistance of SiNW transistors (SNWTs). By transferring the as-fabricated SiNWs onto a plastic substrate, p-SNWTs were fabricated on a plastic substrate, and carrier transport in p-SNWTs was investigated by extracting electrical parameters using the Y Phi method, which include mobility attenuation factors, parasitic series resistance (R-sd), and effective channel resistance. It is shown that, in the strong inversion region, the parameters fit the measurement data well and that degradation in device performance in our p-SNWTs under high transverse electric fields is dominated by surface roughness scattering, with minimal R-sd impact on it due to the relatively thick S/D regions. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4747812]
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공과대학 (전기전자공학부)
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