Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kong, Joonho | - |
dc.contributor.author | Pan, Yan | - |
dc.contributor.author | Ozdemir, Serkan | - |
dc.contributor.author | Mohan, Anitha | - |
dc.contributor.author | Memik, Gokhan | - |
dc.contributor.author | Chung, Sung Woo | - |
dc.date.accessioned | 2021-09-06T17:27:54Z | - |
dc.date.available | 2021-09-06T17:27:54Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2012-08 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/107882 | - |
dc.description.abstract | Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 83.1% of the yield losses. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | LEAKAGE | - |
dc.title | Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Chung, Sung Woo | - |
dc.identifier.doi | 10.1109/TVLSI.2011.2159634 | - |
dc.identifier.scopusid | 2-s2.0-84862685723 | - |
dc.identifier.wosid | 000305605800018 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.8, pp.1532 - 1536 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 20 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 1532 | - |
dc.citation.endPage | 1536 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | LEAKAGE | - |
dc.subject.keywordAuthor | Cache | - |
dc.subject.keywordAuthor | process variation | - |
dc.subject.keywordAuthor | selective wordline voltage boosting | - |
dc.subject.keywordAuthor | supply voltage lowering | - |
dc.subject.keywordAuthor | yield | - |
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