Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations
- Authors
- Kong, Joonho; Pan, Yan; Ozdemir, Serkan; Mohan, Anitha; Memik, Gokhan; Chung, Sung Woo
- Issue Date
- 8월-2012
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Cache; process variation; selective wordline voltage boosting; supply voltage lowering; yield
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.8, pp.1532 - 1536
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 20
- Number
- 8
- Start Page
- 1532
- End Page
- 1536
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/107882
- DOI
- 10.1109/TVLSI.2011.2159634
- ISSN
- 1063-8210
- Abstract
- Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 83.1% of the yield losses.
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Collections - Graduate School > Department of Computer Science and Engineering > 1. Journal Articles
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