A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile
DC Field | Value | Language |
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dc.contributor.author | Hwang, Sewook | - |
dc.contributor.author | Song, Minyoung | - |
dc.contributor.author | Kwak, Young-Ho | - |
dc.contributor.author | Jung, Inhwa | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-06T20:20:52Z | - |
dc.date.available | 2021-09-06T20:20:52Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2012-05 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/108533 | - |
dc.description.abstract | A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH Delta Sigma modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of to +/- 0.5% to 3.5% in steps of 0.5% and three modulation frequencies of f(m), 2f(m) and 3f(m). It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 mm(2) in a 0.13-mu m CMOS process and consuming 23.72 mW at 3.5 GHz. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | TO-VOLTAGE CONVERTER | - |
dc.subject | INTERFERENCE | - |
dc.subject | DESIGN | - |
dc.title | A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/JSSC.2012.2183970 | - |
dc.identifier.wosid | 000303329600014 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.47, no.5, pp.1199 - 1208 | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 47 | - |
dc.citation.number | 5 | - |
dc.citation.startPage | 1199 | - |
dc.citation.endPage | 1208 | - |
dc.type.rims | ART | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | TO-VOLTAGE CONVERTER | - |
dc.subject.keywordPlus | INTERFERENCE | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordAuthor | Double binary-weighted DAC | - |
dc.subject.keywordAuthor | EMI reduction | - |
dc.subject.keywordAuthor | frequency modulation | - |
dc.subject.keywordAuthor | frequency-locked loop (FLL) | - |
dc.subject.keywordAuthor | frequency-to-voltage converter (FVC) | - |
dc.subject.keywordAuthor | Newton-Raphson modulation profile | - |
dc.subject.keywordAuthor | nonlinear profile | - |
dc.subject.keywordAuthor | spread-spectrum clock generator (SSCG) | - |
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