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A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile

Authors
Hwang, SewookSong, MinyoungKwak, Young-HoJung, InhwaKim, Chulwoo
Issue Date
5월-2012
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Double binary-weighted DAC; EMI reduction; frequency modulation; frequency-locked loop (FLL); frequency-to-voltage converter (FVC); Newton-Raphson modulation profile; nonlinear profile; spread-spectrum clock generator (SSCG)
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.47, no.5, pp.1199 - 1208
Indexed
SCIE
SCOPUS
Journal Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume
47
Number
5
Start Page
1199
End Page
1208
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/108533
DOI
10.1109/JSSC.2012.2183970
ISSN
0018-9200
Abstract
A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH Delta Sigma modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of to +/- 0.5% to 3.5% in steps of 0.5% and three modulation frequencies of f(m), 2f(m) and 3f(m). It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 mm(2) in a 0.13-mu m CMOS process and consuming 23.72 mW at 3.5 GHz.
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