PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration

Abstract

A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only +/- 2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm(2) and consumes 94.9 mu W at a supply voltage of 1.0 V.