PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration
- Authors
- Kim, Moo-Young; Lee, Hokyu; Kim, Chulwoo
- Issue Date
- 4월-2012
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- All digital gates; current source; on-chip; process, supply voltage, and temperature (PVT) detector; self-calibration
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.4, pp.737 - 741
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 20
- Number
- 4
- Start Page
- 737
- End Page
- 741
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/108880
- DOI
- 10.1109/TVLSI.2011.2109971
- ISSN
- 1063-8210
- Abstract
- A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only +/- 2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm(2) and consumes 94.9 mu W at a supply voltage of 1.0 V.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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