A Jitter and Power Analysis on DCO
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Doo-Chan | - |
dc.contributor.author | Kim, Kyu-Young | - |
dc.contributor.author | Min, Young-Jae | - |
dc.contributor.author | Park, Jongsun | - |
dc.contributor.author | Kim, Soo-Won | - |
dc.date.accessioned | 2021-09-07T08:38:11Z | - |
dc.date.available | 2021-09-07T08:38:11Z | - |
dc.date.created | 2021-06-19 | - |
dc.date.issued | 2011-09 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/111616 | - |
dc.description.abstract | A jitter and power analysis on a digitally controlled oscillator (DCO) is presented in this brief. By analyzing variable capacitance components on each switching node of the DCO, a simple jitter and power model was derived in a closed form. The proposed mathematical analysis can be effectively used for the accurate and faster estimation of the DCO jitter and power consumption; thus, the overall DCO design time can be significantly reduced. In order to validate our proposed mathematical modeling, the DCO has been designed and fabricated using a 0.13-mu m 1.2-V CMOS process. The fabricated chip presents the root-mean-square and peak-to-peak jitters of 8.9 and 70 ps, respectively, at the output frequency of 600 MHz, under the operation range of 179-656 MHz with a 2.8-ps resolution, which clearly shows that our proposed modeling is well matched with the experimental results. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DIGITALLY CONTROLLED OSCILLATOR | - |
dc.subject | PLL | - |
dc.title | A Jitter and Power Analysis on DCO | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Min, Young-Jae | - |
dc.contributor.affiliatedAuthor | Park, Jongsun | - |
dc.contributor.affiliatedAuthor | Kim, Soo-Won | - |
dc.identifier.doi | 10.1109/TCSII.2011.2161161 | - |
dc.identifier.scopusid | 2-s2.0-80052873057 | - |
dc.identifier.wosid | 000294894900004 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.58, no.9, pp.560 - 564 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.volume | 58 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 560 | - |
dc.citation.endPage | 564 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | DIGITALLY CONTROLLED OSCILLATOR | - |
dc.subject.keywordPlus | PLL | - |
dc.subject.keywordAuthor | All-digital phase-locked loop (ADPLL) | - |
dc.subject.keywordAuthor | clock generator | - |
dc.subject.keywordAuthor | digitally controlled oscillator (DCO) | - |
dc.subject.keywordAuthor | jitter | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
(02841) 서울특별시 성북구 안암로 14502-3290-1114
COPYRIGHT © 2021 Korea University. All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.