10-bit 100-MS/s Pipelined ADC Using Input-Swapped Opamp Sharing and Self-Calibrated V/I Converter
- Authors
- Kim, Moo-Young; Kim, Jinwoo; Lee, Tagjong; Kim, Chulwoo
- Issue Date
- 8월-2011
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Opamp-sharing; pipelined analog-to-digital converter (ADC); self-calibration; switched bias; V/I converter
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.19, no.8, pp.1438 - 1447
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 19
- Number
- 8
- Start Page
- 1438
- End Page
- 1447
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/111837
- DOI
- 10.1109/TVLSI.2010.2050915
- ISSN
- 1063-8210
- Abstract
- A 31 mW, 10-bit 100-MS/s pipelined analog-to-digital converter (ADC), which alleviates the memory effect occurring in the opamp-sharing technique, and automatically corrects the current error of the V/I converter, has been developed. The proposed ADC achieves low-power consumption, high noise immunity, and has a small area, by employing an input-swapped opamp-sharing technique that switches the summing node in an multiplying digital-to-analog converter and a V/I converter with a process, supply voltage, and temperature condition detector. The ADC shows a differential nonlinearity of less than 0.48 LSB, and an integral nonlinearity of less than 0.95 LSB. Also, an signal-to-noise-and-distortion ratio of 56.2 dB is measured with a 1 MHz input frequency. This has been implemented in a 0.18-mu m CMOS process, and occupies 1.6 x 0.8 mm(2) of active area.
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