Leakage current mechanisms in sub-50 nm recess-channel-type DRAM cell transistors with three-terminal gate-controlled diodes
DC Field | Value | Language |
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dc.contributor.author | Chung, Eun-Ae | - |
dc.contributor.author | Kim, Young-Pil | - |
dc.contributor.author | Nam, Kab-Jin | - |
dc.contributor.author | Lee, Sungsam | - |
dc.contributor.author | Min, Ji-Young | - |
dc.contributor.author | Shin, Yu-Gyun | - |
dc.contributor.author | Choi, Siyoung | - |
dc.contributor.author | Jin, Gyoyoung | - |
dc.contributor.author | Moon, Joo-Tae | - |
dc.contributor.author | Kim, Sangsig | - |
dc.date.accessioned | 2021-09-07T15:53:07Z | - |
dc.date.available | 2021-09-07T15:53:07Z | - |
dc.date.created | 2021-06-14 | - |
dc.date.issued | 2011-02 | - |
dc.identifier.issn | 0038-1101 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/113214 | - |
dc.description.abstract | We investigated the leakage mechanism in the recently developed DRAM cell transistors having deeply recessed channels for sub-50 nm technology using a gate-controlled diode method. The identification and modeling of the various leakage components in DRAM cell transistors with three-dimensional structures is of great importance for the estimation of their data retention characteristics. Our study reveals that there is a significant difference in the leakage mechanisms of planar and recessed channel MOSFETs, due to their different geometrical aspects. The leakage current at the extended gate-drain overlapping region in recessed channel MOSFETs is of particular importance from the viewpoint of their refresh modeling. The information on the leakage characteristics of three-dimensional DRAM cell transistors obtained herein will be very useful for refresh modeling and future DRAM device designs. (C) 2010 Published by Elsevier Ltd. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | PERGAMON-ELSEVIER SCIENCE LTD | - |
dc.title | Leakage current mechanisms in sub-50 nm recess-channel-type DRAM cell transistors with three-terminal gate-controlled diodes | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Sangsig | - |
dc.identifier.doi | 10.1016/j.sse.2010.10.004 | - |
dc.identifier.scopusid | 2-s2.0-78751649963 | - |
dc.identifier.wosid | 000287272000040 | - |
dc.identifier.bibliographicCitation | SOLID-STATE ELECTRONICS, v.56, no.1, pp.219 - 222 | - |
dc.relation.isPartOf | SOLID-STATE ELECTRONICS | - |
dc.citation.title | SOLID-STATE ELECTRONICS | - |
dc.citation.volume | 56 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 219 | - |
dc.citation.endPage | 222 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.relation.journalWebOfScienceCategory | Physics, Condensed Matter | - |
dc.subject.keywordAuthor | Gate-controlled diode | - |
dc.subject.keywordAuthor | Leakage current | - |
dc.subject.keywordAuthor | Cell transistor | - |
dc.subject.keywordAuthor | RCAT | - |
dc.subject.keywordAuthor | MOSFET | - |
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