Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chang, I. J. | - |
dc.contributor.author | Park, J. | - |
dc.contributor.author | Kang, K. | - |
dc.contributor.author | Roy, K. | - |
dc.date.accessioned | 2021-09-07T23:20:46Z | - |
dc.date.available | 2021-09-07T23:20:46Z | - |
dc.date.created | 2021-06-14 | - |
dc.date.issued | 2010-11 | - |
dc.identifier.issn | 1751-858X | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/115458 | - |
dc.description.abstract | Owing to increase in parametric variations with technology scaling, accurate estimation of bit-cell failure probability in nano-scale static random access memory (SRAM) has become an extremely challenging task. In this study, the authors propose a method to detect the SRAM bit-cell failure, named 'critical point sampling'. Using this technique, read and hold failure probability of an SRAM bit-cell can be efficiently estimated in a simulation-based way. Simulation results show that our estimation method provides high accuracy, while being similar to 50x faster in computational speed compared to transient Monte-Carlo simulation. The method can be applied to optimise SRAM design for better yield and contributes significantly in reducing the overall design time. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
dc.subject | FLUCTUATIONS | - |
dc.subject | STABILITY | - |
dc.subject | CMOS | - |
dc.title | Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, J. | - |
dc.identifier.doi | 10.1049/iet-cds.2010.0137 | - |
dc.identifier.scopusid | 2-s2.0-78149374043 | - |
dc.identifier.wosid | 000283849200001 | - |
dc.identifier.bibliographicCitation | IET CIRCUITS DEVICES & SYSTEMS, v.4, no.6, pp.469 - 478 | - |
dc.relation.isPartOf | IET CIRCUITS DEVICES & SYSTEMS | - |
dc.citation.title | IET CIRCUITS DEVICES & SYSTEMS | - |
dc.citation.volume | 4 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 469 | - |
dc.citation.endPage | 478 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | FLUCTUATIONS | - |
dc.subject.keywordPlus | STABILITY | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordAuthor | SRAM | - |
dc.subject.keywordAuthor | SRAM failure analysis | - |
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