ACCELERATING JAVA INTERPRETATION IN LOW-COST EMBEDDED PROCESSORS

Abstract

Hardware interpretation is an attractive choice for implementing the Java virtual machine (JVM) in low-end embedded systems. However, the hardware interpretation of complex bytecodes is so expensive that most low-end embedded systems rely on slow software interpreters in processing complex bytecodes. This paper proposes a low-cost hardware approach for accelerating the interpretation of eight complex bytecodes: four object manipulation and four method invocation bytecodes. The proposed approach occupies 204 LUTs in a Xilinx FPGA and reduces by up to 61.5% the number of instructions executed in running the benchmarks considered in this paper.