Energy Efficient Hardware Architecture of LU Triangularization for MIMO Receiver
- Authors
- Choi, Ji-Woong; Lee, Jungwon; Min, Byung Gueon; Park, Jongsun
- Issue Date
- 8월-2010
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Low-power very large scale integration (VLSI) design; LU triangularization; matrix decomposition; multi-input-multi-output (MIMO) demodulation
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.57, no.8, pp.632 - 636
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 57
- Number
- 8
- Start Page
- 632
- End Page
- 636
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/115966
- DOI
- 10.1109/TCSII.2010.2055991
- ISSN
- 1549-7747
- Abstract
- An energy-efficient hardware architecture of complex-valued matrix lower-upper (LU) triangularization for multi-input-multi-output (MIMO) receivers is presented in this paper. In the LU triangularization process, Gaussian elimination operation is expressed as a series of vector-scalar products, where basic common computations can be precomputed and shared to reduce computational complexity. Our computation-sharing-based architecture was implemented using a 0.25-mu m CMOS process, and the hardware can perform LU triangularization from 2 X 2 to 8 X 8 matrices. Numerical results show that the proposed architecture has considerable energy savings over conventional matrix triangularization schemes.
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