8 mW 1.65-Gbps continuous-time equalizer with clock attenuation detection for digital display interface
- Authors
- Kim, Kyu-Young; Lee, Woo-Kwan; Yoo, Jae-Tack; Kim, Soo-Won
- Issue Date
- 5월-2010
- Publisher
- SPRINGER
- Keywords
- Continuous-time equalizer; Equalizer filter; Attenuation detection; Digital display interface; D flip-flop
- Citation
- ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, v.63, no.2, pp.329 - 337
- Indexed
- SCIE
SCOPUS
- Journal Title
- ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
- Volume
- 63
- Number
- 2
- Start Page
- 329
- End Page
- 337
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/116549
- DOI
- 10.1007/s10470-009-9405-8
- ISSN
- 0925-1030
- Abstract
- This paper presents a continuous-time equalizer which provides a low-power, small area and low-cost solution for a DDI implementation. Proposed equalizer adopts clock attenuation detector, enabling one to eliminate complex-and-large feed-back loops, and to achieve compact design and low-power consumption. Using the attenuation signal to all four adaptive equalizer filters composed of three signal channels and a clock channel, one curtails three adaptive attenuation detectors in a multi-channel DDI. The design was done in 0.18-mu m CMOS technology. Experimental results summarize that this equalizer can compensate up to -33 dB channel attenuation at 1.65-Gbps DDI rate, showing eye-width of 0.70 UI. Its average power consumption is 8 mW and the effective area is 0.127 mm(2). This power consumption is very low in comparison to those of previous researches and the effective area is very small.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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