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Hydrogen passivation effects under negative bias temperature instability stress in metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon capacitors for flash memories

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dc.contributor.authorKim, Hee-Dong-
dc.contributor.authorAn, Ho-Myoung-
dc.contributor.authorSeo, Yujeong-
dc.contributor.authorZhang, Yongjie-
dc.contributor.authorPark, Jong Sun-
dc.contributor.authorKim, Tae Geun-
dc.date.accessioned2021-09-08T05:56:38Z-
dc.date.available2021-09-08T05:56:38Z-
dc.date.created2021-06-11-
dc.date.issued2010-01-
dc.identifier.issn0026-2714-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/117208-
dc.description.abstractThe paper presents the passivation effect of post-annealing gases on the negative bias temperature instability of metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon (MONOS) capacitors. MONOS samples annealed at 850 degrees C for 30 s by a rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing gases N-2 and N-2-H-2 (2% hydrogen and 98% nitrogen gas mixture) at 450 degrees C for 30 min. MONOS samples annealed in an N-2-H-2 environment are found to have lowest oxide trap charge density shift, Delta N-or = 8.56 x 10(11)cm(-2), and the lowest interface-trap density increase, Delta N-it = 4.49 x 10(11) cm(-2) among the three samples as-deposited, annealed in N-2 and N-2-H-2 environments. It has also been confirmed that the same MONOS samples have the lowest interface-trap density, D-it = 0.834 x 10(11) eV(-1) cm(-2), using small pulse deep level transient spectroscopy. These results indicate that the density of interface traps between the silicon substrate and the tunneling oxide layer are significantly reduced by the additional furnace annealing in the N-2-H-2 environment after the RTA. (C) 2009 Elsevier Ltd. All rights reserved.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherPERGAMON-ELSEVIER SCIENCE LTD-
dc.subjectINTERFACE STATES-
dc.subjectSONOS-
dc.subjectDEVICE-
dc.subjectSIO2-
dc.titleHydrogen passivation effects under negative bias temperature instability stress in metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon capacitors for flash memories-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Tae Geun-
dc.identifier.doi10.1016/j.microrel.2009.09.008-
dc.identifier.scopusid2-s2.0-72449127023-
dc.identifier.wosid000274610400002-
dc.identifier.bibliographicCitationMICROELECTRONICS RELIABILITY, v.50, no.1, pp.21 - 25-
dc.relation.isPartOfMICROELECTRONICS RELIABILITY-
dc.citation.titleMICROELECTRONICS RELIABILITY-
dc.citation.volume50-
dc.citation.number1-
dc.citation.startPage21-
dc.citation.endPage25-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaScience & Technology - Other Topics-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryNanoscience & Nanotechnology-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.subject.keywordPlusINTERFACE STATES-
dc.subject.keywordPlusSONOS-
dc.subject.keywordPlusDEVICE-
dc.subject.keywordPlusSIO2-
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