A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Moo-Young | - |
dc.contributor.author | Shin, Dongsuk | - |
dc.contributor.author | Chae, Hyunsoo | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-08T13:19:57Z | - |
dc.date.available | 2021-09-08T13:19:57Z | - |
dc.date.created | 2021-06-11 | - |
dc.date.issued | 2009-10 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/119281 | - |
dc.description.abstract | A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mu m CMOS process and, occupies an active area of 170 mu m x 120 mu m. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DLL | - |
dc.title | A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/TVLSI.2008.2004591 | - |
dc.identifier.scopusid | 2-s2.0-70349751726 | - |
dc.identifier.wosid | 000270037400008 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.17, no.10, pp.1461 - 1469 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 17 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 1461 | - |
dc.citation.endPage | 1469 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | DLL | - |
dc.subject.keywordAuthor | Clock generator | - |
dc.subject.keywordAuthor | clock-on-demand | - |
dc.subject.keywordAuthor | lock time | - |
dc.subject.keywordAuthor | PLL | - |
dc.subject.keywordAuthor | portable | - |
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