A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time
- Authors
- Kim, Moo-Young; Shin, Dongsuk; Chae, Hyunsoo; Kim, Chulwoo
- Issue Date
- 10월-2009
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Clock generator; clock-on-demand; lock time; PLL; portable
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.17, no.10, pp.1461 - 1469
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 17
- Number
- 10
- Start Page
- 1461
- End Page
- 1469
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/119281
- DOI
- 10.1109/TVLSI.2008.2004591
- ISSN
- 1063-8210
- Abstract
- A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mu m CMOS process and, occupies an active area of 170 mu m x 120 mu m. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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